1. Field of the Invention
The invention pertains generally to computer circuitry. In particular, it pertains to charge pump circuitry.
2. Description of the Related Art
A charge pump circuit provides an output voltage that is higher than its own supply voltage. Among other uses, charges pumps find application in flash memories to produce erase and program voltages, which are typically several times higher than the supply voltage for the remaining circuitry in the flash memory.
A typical charge pump xe2x80x9cstagexe2x80x9d is a circuit that provides an output voltage that is approximately equal to the sum of the stage""s input voltage and supply voltage. Higher voltages can be obtained by cascading a series of stages, with the output of one stage feeding the input of the next stage. In this manner, the final output voltage of the circuit can be increased to the desired level simply by placing the required number of stages in series. By tapping into this series of stages at different points, various output voltages can be obtained from the same charge pump circuit. Alternately, tapping into this series of stages at different points can produce the same output voltage when the supply voltage is changed, permitting changes in Vcc without requiring a different charge pump circuit to produce the same high voltages.
FIG. 1 shows a schematic of a reconfigurable charge pump circuit 1 that can be reconfigured from a single eight-stage charge pump circuit to a pair of parallel four-stage circuits. The first four stages form a first charge pump section 2, followed by an output circuit 3. The next four stages form a second charge pump section 4, followed by an output circuit 5. Switch circuit 6, shown as a level-shifter circuit, provides the ability to reconfigure from a single eight stage charge pump circuit to a pair of four-stage charge pump circuits in parallel by switching the input of the fifth stage between Y4 (for eight stages) and Vcc (for parallel four-stage sections). Depending on the polarity of select signal SEL, dual-output buffer B1 delivers a high signal to transistor T12 and a low signal to transistor T13, or vice-versa. This connects one of Y4 or Vcc to the input of the fifth stage, thus determining the starting voltage of the second section. This in turn determines whether the output of the second section will be the same as, or higher than, the output of the first section.
In a typical charge pump circuit, each stage has a switchable diode formed from two transistors Txa and Txb (where xe2x80x9cxxe2x80x9d is the stage number). Each stage also has two capacitors Cxa and Cxb, and produces an output voltage Yx. Output circuit regulates the output of the second section, permitting current to pass from Y8 to VOUT when CLK1 is high (turning on transistor T10b), and preventing current from flowing from VOUT back to Y8 when CLK1 is low (turning off transistor T10b). Output circuit 3 performs a similar function for Y4.
FIG. 2 shows a timing diagram for some of the stages of FIG. 1, and can be extrapolated to explain the remaining stages. Each stage produces a similar waveform at Yx, but the voltage level at Yx is increased at each stage by an amount xe2x80x9cVxe2x80x9d. The odd-numbered stage outputs Y1, Y3, Y5 and Y7 all have the same phase relationship to clock signals CLK1-4, while the even numbered stage outputs Y2, Y4, Y6 and Y8 are 180 degrees out of phase with the odd numbered stage outputs. The details of the operation of a charge pump stage are well known and are not further described here.
Output circuit 5 produces the waveform shown in FIG. 2 as VOUT, shown superimposed over the waveform at Y8. When the charge pump circuit 1 is configured as two parallel charge pump circuits, the voltage levels at Y4 and Y8 are virtually identical. When configured as a single eight-stage charge pump circuit, the voltage at Y8 is significantly higher than at Y4.
This arrangement works fairly well when configured as two parallel four-stage charge pump circuits. Since both Y4 and Y8 have the same waveform, phase, and voltage level, their respective currents can be summed at VOUT. However, when configured as a single eight-stage circuit, the voltage at Y8 (and therefore at VOUT) is considerably higher than at Y4. When CLK1 is low, transistor T10b is off, preventing any reverse current flow through it due to this voltage difference. But when CLK1 is high, transistor T10b is on, allowing current to flow in the reverse direction through transistor T10b from the higher voltage VOUT to the lower voltage Y4. This reverse current flow takes available current away from any output load that might be connected to VOUT, and can reduce the voltage level of VOUT by diverting some of the current from output circuit 5 into output circuit 3, current that would otherwise be used to build up the peak value of VOUT. Also, the operation of clock signal CLK1 can cause further inefficiencies within the circuitry of output circuit 3 due to the charging and discharging of capacitor C10, a component that is not even necessary in the eight-stage configuration.